1. Field of the Invention
The present invention relates to a low resistive polysilicon gate electrode for MIS semiconductor devices.
2. Description of the Related Art
MOS transistors are under a practical use with a gate length of 0.8-0.5 .mu.m for high integration and high speed operation of LSI. A trend is a further reduction in gate length.
A buried channel type transistor using an n(+)-polysilicon gate electrode of n type conduction is conventionally used as a p-channel transistor constituting a CMOS.
The further reduction in gate length requires use of surface channel transistor structure using a p(+)-polysilicon gate electrode of p type conduction to restrain punch-through.
There are two problems to be solved in the above-mentioned p(+)-polysilicon gate:
(1) Boron doping is necessary for p type conduction in a polysilicon gate layer. However, since boron has a larger diffusion coefficient than phosphorus conventionally used, the boron diffuses in the gate insulation layer constituting a MOS transistor to enter a semiconductor layer, which changes device characteristics. PA1 (2) If a doping amount of boron is to be reduced in the polysilicon gate layer to give a solution to the above problem of (1), a resistance of gate electrode itself would increase, which is problematic in high speed operation of device. PA1 (1) Increase in activation rate of doped impurities; and PA1 (2) Increase in carrier mobility.
As explained, there are contradicting demands to be met, to lower the resistance while to restrain the diffusion of boron in the boron-doped p(+)-polysilicon gate electrode.